tda9102c selection vs horizontal duty cycle by michel guillien technical note contents page i. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ii. duty cycle calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ii.1. duty min. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ii.2. duty max.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ii.3. typical limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 iii. application for increasing the duty cycle of a tda9102c . . . . . . . . . . 5 iii.1. standard application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 iii.1.1. modified application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 iii.1.2. components calculation in modified application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 iii.1.3. summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 iv. application for decreasing the duty cycle of a tda9102c . . . . . . . . . 6 iv.1. standard application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 iv.1.1. modified application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 iv.1.2. components calculation in modified application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v. conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 i. introduction the tda9102c is a horizontal and vertical deflec- tion processor particularly well suited for high end monitors. one of the key parameters is the very low jitter of the horizontal deflection processor. the horizontal duty cycle is the ratio between the time during which the line switc hing transis tor re- ceives an off command and the line period. as the monitors are using more and more various and higher line frequencies, this duty cycle must be well adapted to the actual application. the following pages show how to calculate the min and max duty cycle for which typical application can work. for the rare cases where the tda 9102c do not fit to the used diagram, a simple application is given, both to increase or to decrease the device duty cycle. it is anyway important to note that the expe- rience shown that in most of the case, when the tda9102c does not fit the application, it is be- cause of too low value. consequently, mainly the application to increase the duty cycle will be used. nota bene : for a quick over view a floppy disk is available using the formulas given here-after and allowing to find at once the right application. for starting the program, just type "9102" AN550/0493 1/8
ii. duty cyle calculation line flyback line deflection current tda9102 line output (pin 7) trace time period t 0 t1 t2 t3 t4 t5 t6 flyback i d1 i t1 t f t d 9102006.eps figure 1 ii.1. duty min. - when the output of the line processor turns low, it takes a time t 1 , before the line switching tran- sistor actually turns off. - then it takes a time t f = t 2 - t 1 for the current in line yoke to invert (fly back time) - as soon as the flyback is finished, the line tran- sistor may be turned on again, although it will actually conduct only when the line current be- comes positive (at t 4 ). thus the minimum off time t d is : t d min = t 1 max + t f max since the duty cycle is defined as t d t where t is the line period : d min = (t 1 max + t f max ) f where f = 1 t so the worst case for d min is at the highest fre- quency used in the monitor : d min = f max (t 1 max + t f max ) (1) t f is usually well know by the designer ; shortening t f is limited by the switching transistor t 1 breakdown voltage. t 1 is the delay between the command for switching off the line transistor t 1 and its actual switching. in diagram 1 and 2, t 1 is the recovery time t r1 of t 1 in diagram 3, t 1 is the recovery time t r1 of t 1 added to the turn on time t o2 of transistor t 2 . so : d min = f max (t r1 max + t f max ) for diagram 1 and 2 d min = f max (t r1 max + t o2 max + tf max for diagram 3 (2) (3) tda9102c selection vs horizontal duty cycle 2/8
t1 v s 6 7 tda9102 d1 9102007.eps diagram 1 : direct drive t1 tda9102 6 7 v s d1 9102008.eps diagram 2 : transformer drive t1 v s 6 7 tda9102 t2 d1 9102009.eps diagram 3 : indirect drive ii.2. duty max. refering to fig 1, the line switching transistor t 1 must be turned on before t 4 , that is to say before the current becomes positive. since it takes a time t o for t 1 to turn on, the command, that is to say the positive going edge of pin 7 must arrive at a time t 3 < t 4 - t o . t 4 would be in the middle of the trace time, at t 2 + t 6 2 , if no energy was lost. since the negative part of the current (from t 2 to t 2 + t 6 2 ) is giving energy back to the power supply while the positive part is drawing energy from it, the latter must be greater. the consequence is that t 4 arrives before the first half of the trace time, say at t 4 = t 2 + k 2 ( t 6 - t 2 ) t 4 = t 2 + k 2 ( t - t f ) k < 1 is an inefficiency factor. this sets the maximum allowable off time t 3 to : t d max = t 3 max = ? ? t 1 + t f + k 2 + ( t - t f ) - t o min ? ? min since the duty cycle is d = t d t = f t d d max = k 2 + ? ? f [t 1 + t f ( 1 - k 2 ) - t o ] ? ? min (4) for applications 1 and 2, t 1 = t r (t 1 turn-off time), t 0 = t o1 (t 1 turn-on time) since for any transistor t r > t o and since k 1, the coefficient of f is always positive. therefore, the worst cas is : d max = k 2 + f min ? t r1 min + t f min ( 1 - k 2 ) - t o1 max ? for applications 1 and 2 (5) for application 3, t r = t r1 + t o2 (t 1 turn-off time + t 2 turn-on time) and t o = t o1 + t r2 (t 1 turn-on time + t 2 turn-off time) normally t 1 is a larger transistor working at a higher current than t 2 so that t r1 + t o2 > t o1 + t r2 and the coefficient of f in (4) is positive. tda9102c selection vs horizontal duty cycle 3/8
in this case : d max = k 2 + f min ? t r1 min + t o2 min + t f min ( 1 - k 2 ) - t o1 max - t r2 max ? min for application 3 (6) however is t 2 is a very cheap transistor versus t 1 , the said coefficient may be negative ; in this case : d max = k 2 - f max ? t o1 max + t r2 max - t f min ( 1 - k 2 ) - t r1 min - t o2 min ? min for application 3 with t r1 + t o2 + t f ( 1 - k 2 ) - t o1 - t r2 < 0 (7) note that in the general case d max worst case is k 2 . this shows that for high frequency application, where equations (2) and (3) show that the duty cycle can not be too small, k needs to be as high as possible. this is why it can be interesting to derive the eht power from a system independant from the deflection one, even for a single frequency terminal. ii.3. typical limits using (2) or (3) and (5) or (6), the allowable limits can be drawn as in fig 2 : f min. f max. d min. d max. duty cycle fixed duty cycle range e q ( 5 ) o r ( 6 ) e q ( 2 ) or ( 3 ) f 9102010.eps figure 2 example : using diagram 1, with t r1 = 2 m s 0.5 m s, t o1 = 0.5 m s, f min = 31.5khz, f max = 56kh, k= 0.95, t f = 2 m s 0.2 m s yields to : (2) : d min = 56 10 3 ( 2.5 + 2.2 ) 10 - 6 = 0.26 (26 %) (5) : d max = 0.95 2 + 31.5 10 3 ? 2 + 1.8 ( 1 - 0.95 2 ) - 0.5 ? 10 - 6 = 0.53 (53 %) tda9102c selection vs horizontal duty cycle 4/8
in this case, tda9102c (35 to 44 %) can be used. at 78khz dmin would be 36.2 %. thus tda9102c would still fit the application. in such applications where it looks safer to center the selected device duty cycle in the allowable duty cycle range, paragraphs iii and iv show a way to increase (resp. decrease) the duty cycle of a tda9102c. iii. application diagram for increasing the duty cycle of a tda9102c this application is needed when the minimum duty cycle of the selected tda 9102c can be lower than the minimum allowable duty cycle of the applica- tion. the latter being proportionnal to f max, the calculations must be done at this max frequency. iii.1. standard application 1 2 r1 c2 v r 1 i 1 i 4 tda9102c 9102011.eps figure 3 v pin 2 t d t r t f t v 1 v 2 v time 9102012.eps figure 4 during rise time t r , a current i 1 , is charging c 2 . this current is the image of the current driven from pin 1 by r 1 : i 1 = v r 2r 1 when the voltage on pin 2 reaches a threshold v 2 , a switch is activated so that the capacitor c 2 is discharged by a current 4i 1 - i 1 = 3i 1 . the fall time t f ends when the threshold value v1 is reached. thus : t r = 2 v 2 - v 1 v r r 1 c 2 t f = 2 v 2 - v 1 v r r 1 c 2 3 t = 8 3 v 2 - v 1 v r r 1 c 2 (8) the off time td is used to define the duty cycle as : duty cycle = t d t the off time is the time during which pin 7 is low. d v is a fixed voltage difference which determines td. t d = 2 d v v r r 1 c 2 (9) mixing (8) and (9) yields to : d v = t d t 4 3 ( v 2 - v 1 ) (9 ) iii.1.1. modified application 1 2 c2 v r tda9102c r'1 r0 1 i' 4 1 i' 9102013.eps figure 5 tda9102c selection vs horizontal duty cycle 5/8
v pin 2 v 1 v 2 v d t' f t' t' r time 2v r r0 r'1 2v r r0 r'1 t' 9102014.eps figure 6 during rise time, a constant voltage drop i 1 r 0 is added to the voltage accross c 2 . during fall time, - 3i 1 r 0 is added. thus the voltage step is 4i 1 r 0 = 2 r 0 v r r 1 the new period can be derived from formula (8), provided the voltage threshold difference v 2 - v 1 is decreased by 2 r 0 v r r 1 hence : t = 8 3 v 2 - v 1 - 2 r 0 r 1 v r v r r 1 c 2 (10) the off time t d is straight foreward : t d = 2 d v v r r 1 c 2 (11) iii.1.2. components calculation in modified application iii.1.2.1. r 1 calculation c 2 is assumed to be constant. equation (ii) shows that fixing a duty cycle, or an off time t d yields to a mandatory r 1 . then equation (10) gives the adequate r 0 value for the given frequency. however the datasheet does not pro- vide d v value, but provides t d t in standard applica- tion (see formula (9)). introducing these known parameters in equation (ii) yields to : t d = 8 3 ( v 2 - v 1 ) v r t d t r 1 c 2 (12) r 1 = 3 8 t d c 2 v r ( v 2 - v 1 ) t t d (13) t d t : device duty cycle, t d : needed off time iii.1.2.2. r 0 calculation using (10) : 3 8 t v r r 1 c 2 = v 2 - v 1 - 2 r 0 r 1 v r 2 r 0 r 1 v r = v 2 - v 1 - 3 8 t v r r 1 c 2 r 0 = v 2 - v 1 v r r 1 2 - 3t 16c 2 (replacing r 1 by (13)) r 0 = 3t 16c 2 ? ? d d - 1 ? ? (14) iii.1.3. summury when the minimum duty cycle t d t of your application is higher than the minimum duty cycle t d t of the chosen device, use the modified application of fig.5, calculating r 1 from (13) and r o from (14). chose the actual values for ro and r, so that a safety margin is allowed for component tolerances. iv. application diagram for decreasing the duty cycle this application is used when the max duty cycle of tda9102c can be higher than the max allowable duty cycle of the application. the latter being pro- portional to f max , the calculation is to be made at f min . iv.1. standard application : please refer to iii t = 8 3 v 2 - v 1 v r r 1 c 2 (8) t d = 2 d v v r r 1 c 2 (9) d v = t d t 4 3 ( v 2 - v 1 ) (9) tda9102c selection vs horizontal duty cycle 6/8
iv.1.1. modified application 1 2 c2 tda9102c r'1 r0 7 d 9102015.eps figure 7 v pin 2 r t f t v 1 v 2 v d t' time t' 9102016.eps figure 8 when the off time td starts, pin 7 is low so that r 0 drives an additional current from pin 1, thus in- creasing the slope on c 2 . if v d is the sum of the saturation voltage on pin 7 and the voltage drop across the diode d, the addi- tional current is : i 0 = v r - v d r 0 since the current charging c 2 is half the current driven from pin 1, the off time is : t d = 2 d v c 2 v r r 1 + v r - v d r 0 (15) using (9) : t d = 8 3 t d t ( v 2 - v 1 ) c 2 v r r 1 + v r - v d r 0 (16) iv.1.2 component calculation of the modified application (fig.5) definitions : td : device off time (normalapplication) d = t d t : device duty cycle td : needed off time (modified application) t : line period (modified application) d = t d t : needed duty cycle v s = v 2 - v 1 : voltage swing at pin 2 (4v) v r : voltage at pin 1 (3.5v) v r = v r - v d : voltage across r 0 during off time ( ? 2.5v) (16) can be rewritten as : t d = 8 3 d v s c 2 v r r 1 + v r r 0 (17) and (9) as (9) d v = 4 3 dv s a second equation is necessary to derive both r 1 and r 0 . it is given by calculating the line period t : refering to fig.6 : t = (t r - t d ) + t d +t f = v s - d v v r 2r 1 c 2 + 8 3 dv s c 2 v r r 1 + v r r 0 + v s c 2 3 v r 2 r 1 tda9102c selection vs horizontal duty cycle 7/8
(9) t t = 2 r 1 v r ? ? ? ? c 2 v s - 4 3 dv s c 2 + 4 3 dv s c 2 1 + v r v r r1 r 0 + c 2 v s 3 ? ? = 8 3 v s v r r 1 c 2 ? ? ? ? 1 - d + d 1 + v r v r r 1 r 0 ? ? = 8 3 v s c 2 v r r 1 + v r r 0 ? ? 1 - d + ( 1 - d ) v r v r r 1 r 0 + d ? ? (17) t t = t d d ? ? 1 + ( 1 - d ) v r v r r 1 r 0 ? ? td t d = 1 + ( 1 - d ) v r v r r 1 r 0 d d - 1 = ( 1 - d ) v r v r r 1 r 0 v r r 0 = v r r 1 d - d d ( 1 - d ) (18) replacing in (17) : t d = 8 3 d v s c 2 v r r 1 ? ? 1 + d - d d ( 1 - d ) ? ? = 8 3 v s c 2 r 1 d ( 1 - d ) v r ( 1 - d ) r 1 = 3 8 t d ( 1 - d ) v r c 2 d ( 1 - d ) v s (19) as d = t d t r 1 = 3 8 t c 2 ( 1 - d ) ( 1 - d ) v r v s (20) using (18) : r 0 = r 1 d ( 1 - d ) ( d - d ) v r v r r 0 = 3 8 t c2 ( 1 - d ) d ( d - d ) v r v s (21) v. conclusion if your maximum allowable duty cycle d is lower than the max duty cycle d of the tda9102c use application of fig.5, calculating r 1 and r 0 from (20) and (21). the tda9102c can be used in virttually all monitor application even though the horizontal duty cycle is basically fixed. this together with the very good jitter figure and all dc controll explains the great succes of this device. information furnished is believed to be accurate and rel iable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - it aly - ja pan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. tda9102c selection vs horizontal duty cycle 8/8
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